电子设计使用verilog语言电子琴实验报告

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电子设计自动化课程设计报告

专业：院系：

指导教师：

2013 年月日

developmentdoes not stop, must adhere to a comprehensive reform does notretreat, must adhere to the strengthening work style building do notslack off,

目

录

1设计目的………………………………………………………32 题目描述与要求………………………………………………33 课程设计报告内容……………………………………………33.1 设计原理与思路……………………………………………33.2 操作过程……………………………………………………43.3 设计和调试过程中出现的问题及解决方法………………74 设计总结和心得体会…………………………………………8

developmentdoes not stop, must adhere to a comprehensive reform does notretreat, must adhere to the strengthening work style building do notslack off,

一、课程设计目的
使用VerilogHDL语言进行前端设计，并使用Quaruts软件在实验箱上实现仿真，实现硬件电子琴。电子琴要求有8个音阶，使用外部时钟信号32MHz，能同步显示音阶。

二、课程设计题目描述和要求
题目：简易电子琴的设计
主要功能：（1）设计一个八音电子琴。

（2）由键盘输入控制音响，同时可自动演奏乐曲。

（3）用户可以将自己编制的乐曲存入电子琴，演奏时可选择键盘输入乐曲或者已存入的乐曲。

三、课程设计报告内容
3.1设计原理与思路
系统由数控分频器、乐曲存储模块以及发声模块组成。数控分频器对FPGA的基准频率进行分频，得到与各个音阶对应的频率输出。乐曲存储模块产生节拍控制和音阶选择信号，即在此模块中可存放一个乐曲曲谱真值表，
由一个计数器来控制此真值表的输出，而由计数器的计数时钟信号作为乐曲节拍控制信号。由发

声模块产生音符对应的频率的信号来使扬声器发音。

（1）模块automusic

developmentdoes not stop, must adhere to a comprehensive reform does notretreat, must adhere to the strengthening work style building do notslack off,

模块automsic由auto信号来选择发声的方式，auto=0时系统自动播放内置的音乐，auto=1时由键盘来手动演奏音乐。

（2）模块TONE
模块Tone是音阶发生器，当8位发声控制输入Index中某一位为高电平时，则对应某一音阶的数值将从端口Tone输出，作为获得该音阶的分频预置值；同时由Code输出对应该音阶简谱的显示数码，如‘5’，并由High输出指示音阶高8度显示。

（3）模块Speaker
模块Speaker中的主要电路是一个数控分频器，它由一个初值可预置的加法计数器构成，当模块Speaker由端口Tone获得一个2进制数后，将以此值为计数器的预置数，对端口Clk12MHZ输入的频率进行分频，之后由Spkout向扬声器

3.2 操作过程输出发声。

新建工程

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添加模块

查找对应芯片

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调试程序

波形仿真

生成逻辑图

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设置管脚

3.3设计和调试过程中出现的问题及解决方法

在初次编写分频模块时候，使用的是比较基本的计数器分频法，编写程序后

在modelsim软件中进行了仿真，发现无法观察到分频情况。经过分析，原因是

由于分频比过大，因此在波形图中很难观察到。而且由于预分频的占空比很小，

developmentdoes not stop, must adhere to a comprehensive reform does notretreat, must adhere to the strengthening work style building do notslack off,

更难以观察到高电平。在原因找到后，为了考察程序的性能，我们将输入频率减小。同时适当缩小分频比，这样就得到了模块仿真中的分频波形。

四、设计总结和心得体会
通过这次课程设计发现，只有理论水平提高了；才能够将课本知识与实践相整合，理论知识服务于教学实践，以增强自己的动手能力。这个实验十分有意义我获得很深刻的经验。通过这次课程设计，我们知道了理论和实际的距离，也知道了理论和实际想结合的重要性，，也从中得知了很多书本上无法得知的知识。

学习不但要立足于书本，以解决理论和实际教学中的实际问题为目的，还要以实学生自己就是一个专家，践相结合，理论问题即实践课题，解决问题即课程研究，
通过自己的手来解决问题比用脑子解决问题更加深刻。
学习就应该采取理论与实践结合的方式，理论的问题，也就是实践性的课题。这种做法既有助于完成理论知识的巩固，又有助于带动实践，解决实际问题，加强我们的动手能力和解决问题的能力。

［1］潘松，《EDA实用教程》，科学出版社，2004年

附录：（源程序）

moduletop(clk32MHz,handTOauto, code1,index1,high1,spkout);

inputclk32MHz,handTOauto; //32MHz 系统时钟,键盘输入/自动演奏input[7:0] index1;//键盘输入信号

output[6:0] code1; //音符显示信号
outputhigh1,spkout;//高低音节信号,音频信号

wire [10:0] tone;
wire [7:0] indx;
automusicu0(.clk(clk32MHz),.index2(index1),.index0(indx),.auto(handTOauto));tone u1(.index(indx),.tone0(tone),.code(code1),.high(high1));

developmentdoes not stop, must adhere to a comprehensive reform does notretreat, must adhere to the strengthening work style building do notslack off,

speakeru2(.clk1(clk32MHz),.tone1(tone),.spks(spkout));

Endmodule

moduleautomusic(clk,auto,index2,index0);//实现自动演奏功能。inputclk,auto;//系统时钟；键盘输入/自动演奏
input [7:0] index2;//键盘输入信号
output[7:0] index0;//音符信号输出

reg[7:0] index0;
reg[4:0] count0;
regclk2;
reg[22:0] count;

always@(clk,auto) //此过程完成对系统时钟8M的分频，得到4Hz的信号clk2begin
if(auto)
begin
count=23'd0;

else if (clk) begin clk2<=1'b1;
end

end

always@(posedge clk2)//此过程完成自动演奏部分曲的地址累加begin
if(count0==5'd31)
count0<=5'd0;
else
count0<=count0+1'b1;
end

always@(count0,auto,index2)
begin
if(!auto)
case(count0) //此case语句：存储自动演奏部分的曲

5'd0: index0<=8'b; //3 5'd1: index0<=8'b;

5'd2: index0<=8'b;

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5'd3: index0<=8'b;
5'd4: index0<=8'b;//5
5'd5: index0<=8'b;
5'd6: index0<=8'b;
5'd7: index0<=8'b;//6
5'd8: index0<=8'b;//8
5'd9: index0<=8'b;
5'd10: index0<=8'b;
5'd11: index0<=8'b;
5'd12: index0<=8'b;//2
5'd13: index0<=8'b;
5'd14: index0<=8'b;//1
5'd15: index0<=8'b;
5'd16: index0<=8'b;//5
5'd17: index0<=8'b;
5'd18: index0<=8'b;//4
5'd19: index0<=8'b;
5'd20: index0<=8'b;
5'd21: index0<=8'b;
5'd22: index0<=8'b;

5'd24: index0<=8'b; 5'd25: index0<=8'b;5'd23: index0<=8'b;

5'd30: index0<=8'b;
5'd31: index0<=8'b;
default: ;
endcase
else index0<=index2; //键盘输入音符信号输出
end
Endmodule

moduletone(index,code,high,tone0); //音阶发生器程序。input[7:0] index;//音符输入信号

output[6:0] code;//音符显示信号
outputhigh;//高低音显示信号

output [10:0] tone0;//音符的分频系数

reg high;

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reg[6:0] code;
reg[10:0] tone0;

always@(index)//此过程完成音符到音符的分频系数译码，音符的显示，高低音阶begin
case(index)
8'b:begin tone0=11'd773; code=6'b;high=1'b1;end
8'b:begin tone0=11'd912; code=6'b;high=1'b1;end
8'b:begin tone0=11'd1116;code=6'b;high=1'b1;end
8'b:begin tone0=11'd1197;code=6'b;high=1'b1;end
8'b:begin tone0=11'd1290;code=6'b;high=1'b0;end
8'b:begin tone0=11'd1372;code=6'b;high=1'b0;end
8'b:begin tone0=11'd1410;code=6'b;high=1'b0;end
default: begin tone0=11'd2047;code=6'b;high=1'b0;end
endcase
end
endmodule

modulespeaker(clk1,tone1, spks);//实现数控分频

output spks;//驱动扬声器的音频信号inputclk1;//系统时钟
input[10:0] tone1;//音符分频系数

reg spks; reg [3:0] count;
reg [10:0] count11;

always @(posedge clk1) //此过程对系统时钟进行4分频
begin
count=count+1'b1;
if (count==4'h2)
preclk<=1'b1;
else
if (count==4'h4)
begin
preclk<=1'b0;
count=4'h0;
end
end

always @(posedge preclk) //此过程按照tone1输入的分频系数对8MHz的脉冲再次分频，

developmentdoes not stop, must adhere to a comprehensive reform does notretreat, must adhere to the strengthening work style building do notslack off,

得到所需要的音符频率
begin
if(count11<tone1)
begin
count11=count11+1;
fullspks<=1'b1;
end
else
begin
count11<=0;
fullspks<=1'b0;
end
end

always@(posedge fullspks) //此进程对fullspks进行2分频begin
count2=~count2;
if(count2)
spks<=1'b1;
else

end Endmodule spks<=1'b0;