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AT6010资料

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Features

•High-performance

–System Speeds > 100 MHz

–Flip-flop Toggle Rates > 250 MHz–1.2 ns/1.5 ns Input Delay–3.0 ns/6.0 ns Output Delay•Up to 204 User I/Os

•Thousands of Registers•

Cache Logic® Design

–Complete/Partial In-System Reconfiguration–No Loss of Data or Machine State–Adaptive Hardware

•Low Voltage and Standard Voltage Operation–5.0 (VCC = 4.75V to 5.25V)–3.3 (V•CC = 3.0V to 3.6V)

Automatic Component Generators

–Reusable Custom Hard Macro Functions•Very Low-power Consumption

–Standby Current of 500 µA/ 200 µA

–Typical Operating Current of 15 to 170 mA•

Programmable Clock Options

–Independently Controlled Column Clocks –Independently Controlled Column Resets –Clock Skew Less Than 1 ns Across Chip•

Independently Configurable I/O (PCI Compatible)–TTL/CMOS Input Thresholds–Open Collector/Tristate Outputs–Programmable Slew-rate Control

–I/O Drive of 16 mA (combinable to mA)

•

Easy Migration to Atmel Gate Arrays for High Volume Production

Description

AT6000 Series SRAM-based Field Programmable Gate Arrays (FPGAs) are ideal foruse as reconfigurable coprocessors and implementing compute-intensive logic.Supporting system speeds greater than 100 MHz and using a typical operating currentof 15 to 170 mA, AT6000 Series devices are ideal for high-speed, compute-intensivedesigns. These FPGAs are designed to implement Cache Logic®, which provides theuser with the ability to implement adaptive hardware and perform hardwareacceleration.

The patented AT6000 Series architecture employs a symmetrical grid of small yetpowerful cells connected to a flexible busing network. Independently controlled clocksand resets govern every column of cells. The array is surrounded by programmableI/O.

(continued)

AT6000 Series Field Programmable Gate Arrays

DeviceAT6002AT6003AT6005AT6010Usable Gates6,0009,00015,00030,000Cells1,0241,6003,1366,400Registers (maximum)1,0241,6003,1366,400I/O (maximum)96120108204Typ. Operating Current (mA)15 - 3025 - 40 - 8085 - 170Cell Rows x Columns32 x 3240 x 4056 x 5680 x 80CoprocessorField Programmable Gate ArraysAT6000(LV) SeriesRev. 02F–10/991

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Devices range in size from 4,000 to 30,000 usable gates,and 1024 to 00 registers. Pin locations are consistentthroughout the AT6000 Series for easy design migration.High-I/O versions are available for the lower gate countdevices.

AT6000 Series FPGAs utilize a reliable 0.6 µm single-poly,double-metal CMOS process and are 100% factory-tested. Atmel's PC- and workstation-based Integrated Develop-ment System is used to create AT6000 Series designs.Multiple design entry methods are supported.

The Atmel architecture was developed to provide the high-est levels of performance, functional density and designflexibility in an FPGA. The cells in the Atmel array aresmall, very efficient and contain the most important andmost commonly used logic and wiring functions. The cell’ssmall size leads to arrays with large numbers of cells,greatly multiplying the functionality in each cell. A simple,high-speed busing network provides fast, efficient commu-nication over medium and long distances.

The Symmetrical Array

At the heart of the Atmel architecture is a symmetrical arrayof identical cells (Figure 1). The array is continuous andcompletely uninterrupted from one edge to the other,except for bus repeaters spaced every eight cells(Figure2).

In addition to logic and storage, cells can also be used aswires to connect functions together over short distancesand are useful for routing in tight spaces.

The Busing Network

There are two kinds of buses: local and express (seeFigures2 and 3).

Local buses are the link between the array of cells and thebusing network. There are two local buses – North-South 1and 2 (NS1 and NS2) – for every column of cells, and twolocal buses – East-West 1 and 2 (EW1 and EW2) – forevery row of cells. In a sector (an 8 x 8 array of cellsenclosed by repeaters) each local bus is connected toevery cell in its column or row, thus providing every cell inthe array with read/write access to two North-South andtwo East-West buses.

Figure 1. Symmetrical Array Surrounded by I/O

AT6000(LV) Series

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AT6000(LV) Series

Figure 2. Busing Network (one sector)

CELLREPEATERFigure 3. Cell-to-cell and Bus-to-bus Connections

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Each cell, in addition, provides the ability to route a signalon a 90° turn between the NS1 bus and EW1 bus andbetween the NS2 bus and EW2 bus.

Express buses are not connected directly to cells, and thusprovide higher speeds. They are the fastest way to coverlong, straight-line distances within the array.

Each express bus is paired with a local bus, so there aretwo express buses for every column and two expressbuses for every row of cells.

Connective units, called repeaters, spaced every eightcells, divide each bus, both local and express, intosegmentsspanning eight cells. Repeaters are aligned inrows and columns thereby partitioning the array into 8 x 8sectors of cells. Each repeater is associated with alocal/express pair, and on each side of the repeater areconnections to a local-bus segment and an express-bussegment. The repeater can be programmed to provide anyone of twenty-one connecting functions. These functionsare symmetric with respect to both the two repeater sidesand the two types of buses.

Among the functions provided are the ability to: •Isolate bus segments from one another•Connect two local-bus segments•Connect two express-bus segments•Implement a local/express transfer

In all of these cases, each connection provides signalregeneration and is thus unidirectional. For bidirectionalconnections, the basic repeater function for the NS2 andEW2 repeaters is augmented with a special programmableconnection allowing bidirectional communication betweenlocal-bus segments. This option is primarily used to imple-ment long, tristate buses.

The Cell Structure

The Atmel cell (Figure 4) is simple and small and yetcanbe programmed to perform all the logic and wiringfunctions needed to implement any digital circuit. Its foursides are functionally identical, so each cell is completelysymmetrical.

Read/write access to the four local buses – NS1, EW1,NS2 and EW2 – is controlled, in part, by four bidirectionalpass gates connected directly to the buses. To read a localbus, the pass gate for that bus is turned on and the three-input multiplexer is set accordingly. To write to a local bus,the pass gate for that bus and the pass gate for the associ-ated tristate driver are both turned on. The two-inputmultiplexer supplying the control signal to the drivers per-mits either: (1) active drive, or (2) dynamic tristatingcontrolled by the B input. Turning between LNS1 and LEW1 orbetween LNS2 and LEW2 is accomplished by turning on thetwo associated pass gates. The operations of reading, writ-ing and turning are subject to the restriction that each buscan be involved in no more than a single operation.

Figure 4. Cell Structure

AT6000(LV) Series

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AT6000(LV) Series

•In State 3 – corresponding to the “3” inputs of the

multiplexers – the XOR function of State 2 is provided to the D input of a D-type flip-flop, the Q output of which is connected to the cell’s A output. Clock and

asynchronous reset signals are supplied externally as described later. The AND of the outputs from the two upstream AND gates is provided to the cell's B output.

In addition to the four local-bus connections, a cell receivestwo inputs and provides two outputs to each of itsNorth(N), South (S), East (E) and West (W) neighbors.These inputs and outputs are divided into two classes: “A”and “B”. There is an A input and a B input from each neigh-boring cell and an A output and a B output driving all fourneighbors. Between cells, an A output is always connectedto an A input and a B output to a B input.

Within the cell, the four A inputs and the four B inputs entertwo separate, independently configurable multiplexers. Cellflexibility is enhanced by allowing each multiplexer to selectalso the logical constant “1”. The two multiplexer outputsenter the two upstream AND gates.

Downstream from these two AND gates are an Exclusive-OR (XOR) gate, a register, an AND gate, an inverter andtwo four-input multiplexers producing the A and B outputs.These multiplexers are controlled in tandem (unlike theAand B input multiplexers) and determine the function ofthe cell.

•In State 0 – corresponding to the “0” inputs of the

multiplexers – the output of the left-hand upstream AND gate is connected to the cell’s A output, and the output of the right-hand upstream AND gate is connected to the cell’s B output.•In State 1 – corresponding to the “1” inputs of the

multiplexers – the output of the left-hand upstream AND gate is connected to the cell’s B output, the output of the right-hand upstream AND gate is connected to the cell’s A output.•In State 2 – corresponding to the “2” inputs of the multiplexers – the XOR of the outputs from the two upstream AND gates is provided to the cell’s A output, while the NAND of these two outputs is provided to the cell’s B output.

Logic States

The Atmel cell implements a rich and powerful set of logicfunctions, stemming from 44 logical cell states which per-mutate into 72 physical states. Some states use both A andB inputs. Other states are created by selecting the “1” inputon either or both of the input multiplexers.

There are 28 combinatorial primitives created from thecell’s tristate capabilities and the 20 physical states repre-sented in Figure 5. Five logical primitives are derived fromthe physical constants shown in Figure 7. More complexfunctions are created by using cells in combination.A two-input AND feeding an XOR (Figure 8) is producedusing a single cell (Figure 9). A two-to-one multiplexerselects the logical constant “0” and feeds it to the right-hand AND gate. The AND gate acts as a feed-through, let-ting the B input pass through to the XOR. The three-to-onemultiplexer on the right side selects the local-bus input,LNS1, and passes it to the left-hand AND gate. The A andLNS1 signals are the inputs to the AND gate. The output ofthe AND gate feeds into the XOR, producing the logic state(AlL) XOR B.

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Figure 5. Combinatorial Physical States

LiLiALiBFigure 7. Physical Constants

\"0\"A,Lo\"0\"B\"0\"A,Lo\"1\"B\"1\"A,Lo\"0\"B\"1\"A,Lo\"1\"BA,LoALiBBA,LoALiBBA,LoALiBA,LoALiBA,LoALiBA,LoBA,LoBA,LoBA,LoBA,LoBFigure 8. Two-input AND Feeding XOR

ALiBLiBLiBLiBALiALiBA,LoBA,LoBBA,LoA,LoA,LoBALiBALiBALi10A,LoBALiBAA,LoBA,LoBA,LoBA,LoBFigure 6. Register States

ADQA,Lo\"0\"BDQA,LoALiBLiBDQA,LoALiBDQA,LoBALiBFigure 9. Cell Configuration (AlL) XOR B

DQDQA,LoABBLiBA,LoDQA,LoALiBALiB10DQA,LoBDQA,LoBDQDQA,LoBA,Lo6

AT6000(LV) Series

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AT6000(LV) Series

Asynchronous Reset

Along the bottom edge of the array is logic for asynchro-nously resetting the D flip-flops in the logic cells(Figure10). Like the clock network, the asynchronous resetnetwork is organized by column and permits columns to beindependently reset. At the bottom of each column is auser-configurable multiplexer providing the reset signal forthat column. It has four inputs:

•Global asynchronous reset supplied through the RESETpin•Express bus adjacent to the distribution logic•“A” output of the cell at the foot of the column•Logical constant “1” to conserve power

The asynchronous reset logic uses these four inputs in thesame way that the clock distribution logic does. Throughthe global asynchronous reset, any or all columns can bereset by an externally supplied signal. The global asynchro-nous reset pin is also connected directly to the array via theA input of the lower left and right corner cells (AS on theleft, and AE on the right). The express bus can be used todistribute a secondary reset to multiple columns when theglobal reset line is used as a primary reset, the A output ofa cell can also provide an asynchronous reset signal to asingle column, and the constant “1” is used by columnswith registers requiring no reset. All registers are reset dur-ing power-up.

Clock Distribution

Along the top edge of the array is logic for distributing clocksignals to the D flip-flop in each logic cell (Figure 10). Thedistribution network is organized by column and permitscolumns of cells to be independently clocked. At the headof each column is a user-configurable multiplexer providingthe clock signal for that column. It has four inputs:•Global clock supplied through the CLOCK pin•Express bus adjacent to the distribution logic•“A” output of the cell at the head of the column•Logical constant “1” to conserve power (no clock)Through the global clock, the network provides low-skewdistribution of an externally supplied clock to any or all ofthe columns of the array. The global clock pin is also con-nected directly to the array via the A input of the upper leftand right corner cells (AW on the left, and AN on the right).The express bus is useful in distributing a secondary clockto multiple columns when the global clock line is used as aprimary clock. The A output of a cell is useful in providing aclock signal to a single column. The constant “1” is used toreduce power dissipation in columns using no registers.Figure 10. Column Clock and Column Reset

GLOBALCLOCK\"1\"GLOBALCLOCKADQEXPRESSBUSCELLEXPRESSBUSDQCELLDEDICATEDInput/Output

The Atmel architecture provides a flexible interfacebetween the logic array, the configuration control logic andthe I/O pins.

Two adjacent cells – an “exit” and an “entrance” cell – onthe perimeter of the logic array are associated with eachI/O pin.

There are two types of I/Os: A-type (Figure 11) and B-type(Figure 12). For A-type I/Os, the edge-facing A output of anexit cell is connected to an output driver, and the edge-facingA input of the adjacent entrance cell is connected toan input buffer. The output of the output driver and the inputof the input buffer are connected to a common pin. B-type I/Os are the same as A-type I/Os, but use the Binputs and outputs of their respective entrance and exitcells. A- and B-type I/Os alternate around the array Controlof the I/O logic is provided by user-configurable memorybits.

BURIEDROUTINGCELLDQEXPRESSBUSCELLDQA\"1\"GLOBALRESETGLOBALRESETEXPRESSBUS7

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Figure 11. A-type I/O LogicSlew Rate Control

A user-configurable bit controls the slew rate – fast or slow– of the output buffer. A slow slew rate, which reducesnoise and ground bounce, is recommended for outputs thatare not speed-critical. Fast and slow slew rates have thesame DC-current sinking capabilities, but the rate at whicheach allows the output devices to reach full drive differs. Pull-up

A user-configurable bit controls the pull-up transistor in theI/O pin. It’s primary function is to provide a logical “1” tounused input pins. When on, it is approximately equivalentto a 25K resistor to VCC.Enable Select

User-configurable bits determine the output-enable for theoutput driver. The output driver can be static – always on oralways off – or dynamically controlled by a signal gener-ated in the array. Four options are available from the array:(1) the control is low and always driving; (2) the control ishigh and never driving; (3) the control is connected to a ver-tical local bus associated with the output cell; or (4) thecontrol is connected to a horizontal local bus associatedwith the output cell. On power-up, the user I/Os are config-ured as inputs with pull-up resistors.

In addition to the functionality provided by the I/O logic, theentrance and exit cells provide the ability to register bothinputs and outputs. Also, these perimeter cells (unlike inte-rior cells) are connected directly to express buses: theedge-facing A and B outputs of the entrance cell are con-nected to express buses, as are the edge-facing A and Binputs of the exit cell. These buses are perpendicular to theedge, and provide a rapid means of bringing I/O signals toand from the array interior and the opposite edge of thechip.

Figure 12. B-type I/O Logic

Chip Configuration

The Integrated Development System generates the SRAMbit pattern required to configure a AT6000 Series device. APC parallel port, microprocessor, EPROM or serial configu-ration memory can be used to download configurationpatterns.

Users select from several configuration modes. Many fac-tors, including board area, configuration speed and thenumber of designs implemented in parallel can influencethe user’s final choice.

Configuration is controlled by dedicated configuration pinsand dual-function pins that double as I/O pins when thedevice is in operation. The number of dual-function pinsrequired for each mode varies.

TTL/CMOS Inputs

A user-configurable bit determines the threshold level –TTL or CMOS – of the input buffer.Open Collector/Tristate Outputs

A user-configurable bit which enables or disables the activepull-up of the output device.

AT6000(LV) Series

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AT6000(LV) Series

M0, M1, M2

Configuration mode pins are used to determine the config-uration mode. All three are TTL input pins.CCLK

Configuration clock pin. CCLK is a TTL input or a CMOSoutput depending on the mode of operation. In modes 1, 2,3, and 6 it is an input. In modes 4 and 5 it is an output witha typical frequency of 1 MHz. In all modes, the rising edgeof the CCLK signal is used to sample inputs and changeoutputs.CLOCK

External logic source used to drive the internal global clockline. Registers toggle on the rising edge of CLOCK. TheCLOCK signal is neither used nor affected by the configu-ration modes. It is always a TTL input.RESETArray register asynchronous reset. RESET drives the inter-nal global reset. The RESET signal is neither used noraffected by the configuration modes. It is always a TTLinput.

Dual-function Pins

When CON is high, dual-function I/O pins act as deviceI/Os; when CON is low, dual-function pins are used as con-figuration control or data signals as determined by theconfiguration modes. Care must be taken when usingthese pins to ensure that configuration activity does notinterfere with other circuitry connected to these pins in theapplication.D0 or I/O

Serial configuration modes use D0 as the serial data inputpin. Parallel configuration modes use D0 as the least-sig-nificant bit. Input data must meet setup and holdrequirements with respect to the rising edge of CCLK. D0 isa TTL input during configuration.D1 to D7 or I/O

Parallel configuration modes use these pins as inputs.Serial configuration modes do not use them. Data mustmeet setup and hold requirements with respect to the risingedge of CCLK. D1 - D7 are TTL inputs during configuration.A0 to A16 or I/O

During configuration in modes 1, 2 and 5, these pins areCMOS outputs and act as the address pins for a parallelEPROM. A0 - A16 eliminates the need for an externaladdress counter when using an external parallel nonvolatile

The devices can be partially reconfigured while in opera-tion. Portions of the device not being modified remainoperational during reconfiguration. Simultaneous configu-ration of more than one device is also possible. Fullconfiguration takes as little as a millisecond, partial configu-ration is even faster.

Refer to the Pin Function Description section following for abrief summary of the pins used in configuration. For moreinformation about configuration, refer to the AT6000 SeriesConfiguration data sheet.

Pin Function Description

This section provides abbreviated descriptions of the vari-ous AT6000 Series pins. For more complete descriptions,refer to the AT6000 Series Configuration data sheet.Pinout tables for the AT6000 series of devices follow.

Power Pins

VCC, VDD, GND, VSS

VCC and GND are the I/O supply pins, VDD and VSS are theinternal logic supply pins. VCC and VDD should be tied to thesame trace on the printed circuit board. GND and VSSshould be tied to the same trace on the printed circuitboard.

Input/Output Pins

All I/O pins can be used in the same way (refer to the I/Osection of the architecture description). Some I/O pins aredual-function pins used during configuration of the array.When not being used for configuration, dual-function I/Osare fully functional as normal I/O pins. On initial power-up,all I/Os are configured as TTL inputs with a pull-up.

Dedicated Timing and Control Pins

CONConfiguration-in-process pin. After power-up, CON stay-sLow until power-up initialization is complete, at which timeCON is then released. CON is an open collector signal.After power-up initialization, forcing CON low begins theconfiguration process.CSConfiguration enable pin. All configuration pins are ignoredif CS is high. CS must be held low throughout the configu-ration process. CS is a TTL input pin.9

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memory to configure the FPGA. Addresses change afterthe rising edge of the CCLK signal.CSOUT or I/OWhen cascading devices, CSOUT is an output used toenable other devices. CSOUT should be connected to theCS input of the downstream device. The CSOUT function isoptional and can be disabled during initial programmingwhen cascading is not used. When cascading devices,CSOUT should be dedicated to configuration and not usedas a configurable I/O.CHECK or I/ODuring configuration, CHECK is a TTL input that can beused to enable the data check function at the beginning ofa configuration cycle. No data is written to the device whileCHECK is low. Instead, the configuration file being appliedto D0 (or D0 - D7, in parallel mode) is compared with the

current contents of the internal configuration RAM. If a mis-match is detected between the data being loaded and thedata already in the RAM, the ERR pin goes low. TheCHECK function is optional and can be disabled during ini-tial programming.ERR or I/ODuring configuration, ERR is an output. When the CHECKfunction is activated and a mismatch is detected betweenthe current configuration data stream and the data alreadyloaded in the configuration RAM, ERR goes low. The ERRouput is a registered signal. Once a mismatch is found, thesignal is set and is only reset after the configuration cycle isrestarted. ERR is also asserted for configuration file errors.The ERR function is optional and can be disabled duringinitial programming.

Device Pinout Selection (Max. Number of User I/O)

AT6002

84 PLCC100 VQFP132 PQFP144 TQFP208 PQFP240 PQFP

I/O80 I/O96 I/O95 I/O--AT6003 I/O80 I/O108 I/O120 I/O--AT6005 I/O80 I/O108 I/O108 I/O--AT6010

--108 I/O120 I/O172 I/O204 I/O

Bit-stream Sizes

Mode(s)

123456

TypeParallelParallelSerialSerialParallelParallel

Beginning SequencePreamblePreamble

Null Byte/PreambleNull Byte/PreamblePreamble

Preamble/Preamble

AT6002267726772678267826772678

AT6003415341534141415341

AT6005807780778078807880778078

AT6010163931639316394163941639316394

AT6000(LV) Series

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AT6000(LV) Series

Pinout Assignment

Left Side (Top to Bottom)

AT6002-I/O24(A) or A7------I/O23(A) or A6--I/O22(B)I/O21(A) or A5--I/O20(B)I/O19(A) or A4-I/O18(B)I/O17(A) or A3I/O16(B)-I/O15(A) or A2-GNDVSS

I/O14(A) or A1--I/O13(A) or A0I/O12(B) or D7-I/O11(A) or D6I/O10(A) or D5VDDVCC

AT6003-I/O30(A) or A7I/O29(B)----I/O28(A)I/O27(A) or A6--I/O26(A)I/O25(A) or A5--I/O24(B)I/O23(A) or A4-I/O22(B)I/O21(A) or A3I/O20(B)-I/O19(A) or A2I/O18(B)GNDVSS

I/O17(A) or A1-I/O16(B)I/O15(A) or A0I/O14(A) or D7-I/O13(A) or D6I/O12(A) or D5VDDVCC

AT6005-I/O27(A) or A7-----I/O26(A)I/O25(A) or A6--I/O24(A)I/O23(A) or A5--I/O22(A)I/O21(A) or A4-I/O20(A)I/O19(A) or A3I/O18(A)-I/O17(A) or A2I/O16(A)GNDVSS

I/O15(A) or A1--I/O14(A) or A0I/O13(A) or D7-I/O12(A) or D6I/O11(A) or D5VDDVCC

AT6010I/O51(A)I/O50(A) or A7I/O49(A)I/O48(B)VCCI/O47(A)GNDI/O46(A)I/O45(A) or A6I/O44(B)I/O43(A)I/O42(A)I/O41(A) or A5I/O40(B)I/O39(A)I/O38(A)I/O37(A) or A4I/O36(B)I/O35(A)I/O34(A) or A3I/O33(A)I/O32(B)I/O31(A) or A2I/O30(A)GNDVSS

I/O29(A) or A1I/O28(B)I/O27(A)I/O26(A) or A0I/O25(B) or D7I/O24(B)I/O23(A) or D6I/O22(A) or D5VDDVCC

84 PLCC-12------13---14---15--16--17-181920--2122-23242526

100 VQFP-1------2---3--45--67-8-91011--1213-14151617

132 PQFP-18-----1920--2122--2324-252627-2829303132--3334-35363738

144 TQFP-12----34--56--78-91011-1213141516-171819-20212223

180 CPGAB1C1D1-PWR(1)E1GND(2)G1H1-C2D2E2-F2G2H2-D3E3F3-G3H3GND(2)GND(2)F4-G4H4H5-J4K4PWR(1)PWR(1)

208 PQFP123-45678-91011-121314-151617181920212223242526272829303132

240 PQFP1234567101112131415161718192021222324252627282930313233343536

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Pinout Assignment (Continued)

Left Side (Top to Bottom)

AT6002I/O9(B)-I/O8(A) or D4I/O7(B)--I/O6(A) or D3--GND--I/O5(A) or D2I/O4(B)--I/O3(A) or D1I/O2(B)---I/O1(A) or D0-CCLK

AT6003I/O11(B)-I/O10(A) or D4I/O9(B)--I/O8(A) or D3I/O7(B)-GND--I/O6(A) or D2I/O5(B)--I/O4(A) or D1I/O3(A)--I/O2(B)I/O1(A) or D0-CCLK

AT6005I/O10(A)-I/O9(A) or D4I/O8(A)--I/O7(A) or D3I/O6(A)-GND--I/O5(A) or D2I/O4(A)--I/O3(A) or D1I/O2(A)---I/O1(A) or D0-CCLK

AT6010I/O21(A)I/O20(B)I/O19(A) or D4I/O18(A)I/O17(A)I/O16(B)I/O15(A) or D3I/O14(A)I/O13(A)GNDVSSI/O12(B)I/O11(A) or D2I/O10(A)I/O9(A)I/O8(B)I/O7(A) or D1I/O6(A)I/O5(A)I/O4(B)I/O3(A)I/O2(A) or D0I/O1(A)CCLK

84 PLCC--27---28-----29---30----31-32

100 VQFP--1819--20-----2122--23----24-25

132 PQFP39-4041--4243-44--46--4748---49-50

144 TQFP24-2526--2728-29--3031--3233--3435-36

180 CPGAJ3-K3L3M3-N3J2K2GND(2)GND(2)

-M2N2P2-J1K1L1-M1N1P1R1

208 PQFP3334353637-3839404142-434445-4748-49505152

240 PQFP373839404142434447484950515253555657585960

Notes:1.PWR = Pins connected to power plane = F1, E4/E5, L2, R4, K15, L12, E14, A12.2.GND = Pins connected to ground plane = L4, M4, N9, N10, E12, D12, C7, C6.

AT6000(LV) Series

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AT6000(LV) Series

Pinout Assignment

Bottom Side (Left to Right)

AT6002CON-I/O96(A)------I/O95(A) or CSOUT--I/O94(B)I/O93(A)--I/O92(B)I/O91(A) or CHECK-I/O90(B)I/O(A) or ERRI/O88(B)-I/O87(A)-GNDI/O86(A)--I/O85(A)CSI/O84(B)-I/O83(A)

AT6003CON-I/O120(A)I/O119(B)----I/O118(A)I/O117(A) or CSOUT--I/O116(A)I/O115(A)--I/O114(B)I/O113(A) or CHECK-I/O112(B)I/O111(A) or ERRI/O110(B)-I/O109(A)I/O108(B)GNDI/O107(A)-I/O106(B)I/O105(A)CSI/O104(A)-I/O103(A)

AT6005CON-I/O108(A)-----I/O107(A)I/O106(A) or CSOUT--I/O105(A)I/O104(A)--I/O103(A)I/O102(A) or CHECK-I/O101(A)I/O100(A) or ERRI/O99(A)-I/O98(A)I/O97(A)GNDI/O96(A)--I/O95(A)CSI/O94(A)-I/O93(A)

AT6010CONI/O204(A)I/O203(A)I/O202(A)I/O201(B)VCCI/O200(A)GNDI/O199(A)I/O198(A) or CSOUTI/O197(B)I/O196(A)I/O195(A)I/O194(A)I/O193(B)I/O192(A)I/O191(A)I/O190(A) or CHECKI/O1(B)I/O188(A)I/O187(A) or ERRI/O186(A)I/O185(B)I/O184(A)I/O183(A)GNDI/O182(A)I/O181(B)I/O180(A)I/O179(A)CSI/O178(A)I/O177(B)I/O176(A)

84 PLCC33-34------35---36---37--38--39-4041--424344-45

100 VQFP26-27------28---29--3031--3233-34-3536--373839-40

132 PQFP51-52-----53--5556--5758-596061-626365--666768-69

144 TQFP37-3839----4041--4243--4445-4748-49505152-535556-57

180 CPGAM5M6M7R2-PWR(1)R3GND(2)R5R6-R7P3P4-P5P6P7-N4N5N6-N7M8GND(2)M9-M10M11L8M12-N8

208 PQFP535556-5758596061-6263-656667-686970717273747576777879808182

240 PQFP61626365666768697071727374757677787980818283848586878091929394

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Pinout Assignment (Continued)

Bottom Side (Left to Right)

AT6002-VCCI/O82(A)I/O81(B)-I/O80(A)I/O79(B)--I/O78(A)--GND-I/O77(A)I/O76(B)--I/O75(A)I/O74(B)---I/O73(A)-RESETAT6003-VCCI/O102(A)I/O101(B)-I/O100(A)I/O99(B)--I/O98(A)I/O97(B)-GND-I/O96(A)I/O95(B)--I/O94(A)I/O93(A)--I/O92(B)I/O91(A)-RESETAT6005-VCCI/O92(A)I/O91(A)-I/O90(A)I/O(A)--I/O88(A)I/O87(A)-GND-I/O86(A)I/O85(A)--I/O84(A)I/O83(A)---I/O82(A)-RESETAT6010VDDVCCI/O175(A)I/O174(A)I/O173(B)I/O172(A)I/O171(A)I/O170(A)I/O169(B)I/O168(A)I/O167(A)I/O166(A)GNDI/O165(B)I/O1(A)I/O163(A)I/O162(A)I/O161(B)I/O160(A)I/O159(A)I/O158(A)I/O157(B)I/O156(A)I/O155(A)I/O1(A)RESET84 PLCC-47--48---49----50---51----52-53

100 VQFP-4142--4344--45----47--48----49-50

132 PQFP-707172-7374--7576-77-7879--8081---82-83

144 TQFP-585960-6162--63-65-6667--6869--7071-72

180 CPGAPWR(1)PWR(1)N11N12-N13P8P9-P10P11P12GND(2)

-P13P14P8-R9R10R11-R12R13R14R15

208 PQFP838485868780-91929394-959697-99100-101102103104

240 PQFP95969799100101102103104105106107108109110111112113114115116117118119120

Notes:

1.PWR = Pins connected to power plane = F1, E4/E5, L2, R4, K15, L12, E14, A12.2.GND = Pins connected to ground plane = L4, M4, N9, N10, E12, D12, C7, C6.

AT6000(LV) Series

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AT6000(LV) Series

Pinout Assignment

Right Side (Bottom to Top)

AT6002-I/O72(A)------I/O71(A)--I/O70(B)I/O69(A)--I/O68(B)I/O67(A)-I/O66(B)I/O65(A)I/O(B)-I/O63(A)-GNDVSSI/O62(A)--I/O61(A)I/O60(B)-I/O59(A)I/O58(A)VDDVCC

AT6003-I/O90(A)I/O(B)----I/O88(A)I/O87(A)--I/O86(A)I/O85(A)--I/O84(B)I/O83(A)-I/O82(B)I/O81(A)I/O80(B)-I/O79(A)I/O78(B)GNDVSSI/O77(A)-I/O76(B)I/O75(A)I/O74(A)-I/O73(A)I/O72(A)VDDVCC

AT6005-I/O81(A)I/O80(A)-----I/O79(A)--I/O78(A)I/O77(A)--I/O76(A)I/O75(A)-I/O74(A)I/O73(A)I/O72(A)-I/O71(AI/O70(A)GNDVSSI/O69(A)--I/O68(A)I/O67(A)-I/O66(A)I/O65(A)VDDVCC

AT6010I/O153(A)I/O152(A)I/O151(A)I/O150(B)VCCI/O149(A)GNDI/O148(A)I/O147(A)I/O146(B)I/O145(A)I/O144(A)I/O143(A)I/O142(B)I/O141(A)I/O140(A)I/O139(A)I/O138BI/O137(A)I/O136(A)I/O135(A)I/O134(B)I/O133(A)I/O132(A)GNDVSSI/O131(A)I/O130(B)I/O129(A)I/O128(A)I/O127(A)I/O126(B)I/O125(A)I/O124(A)VDDVCC

84 PLCC-------55---56---57--58--59-606162--63-65666768

100 VQFP-51------52---53--55--5657-58-596061--6263-656667

132 PQFP-8485(3)----85(4)86--8788--90-919293-9495969798--99100-101102103104

144 TQFP-7374----7576--7778--7980-818283-8485868788-9091-92939495

180 CPGAP15N15M15-PWR(1)L15GND(2)J15H15-N14M14L14-K14J14H14-M13L13K13-J13H13GND(2)GND(2)K12-J12H12H11-G12F12PWR(1)PWR(1)

208 PQFP105106107-108109110111112-113114115-116117118-119120121122123124125126127128129130131132133134135136

240 PQFP1211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531155156

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Pinout Assignment (Continued)

Right Side (Bottom to Top)

AT6002I/O57(B)-I/O56(A)I/O55(B)--I/O(A)--GND--I/O53(A)I/O52(B)--I/O51(A)I/O50(B)---I/O49(A)-M2

AT6003I/O71(B)-I/O70(A)I/O69(B)--I/O68(A)I/O67(B)-GND--I/O66(A)I/O65(B)--I/O(A)I/O63(A)--I/O62(B)I/O61(A)-M2

AT6005I/O(A)-I/O63(A)I/O62(A)--I/O61(A)I/O60(A)-GND--I/O59(A)I/O58(A)--I/O57(A)I/O56(A)---I/O55(A)-M2

AT6010I/O123(A)I/O122(B)I/O121(A)I/O120(A)I/O119(A)I/O118(B)I/O117(A)I/O116(A)I/O115(A)GNDVSSI/O114(B)I/O113(A)I/O112(A)I/O111(A)I/O110(B)I/O109(A)I/O108(A)I/O107(A)I/O106(B)I/O105(A)I/O104(A)I/O103(A)M2

84 PLCC--69---70-----71---72----73-74

100 VQFP--6869--70-----7172--73----74-75

132 PQFP105-106107--108109-110--111112--113114---115-116

144 TQFP96-9798--99100-101--102103--104105--106107-108

180 CPGAG13-F13E13D13-C13G14F14GND(2)GND(2)

-D14C14B14-G15F15E15-D15C15B15A15

208 PQFP137138139140141-142143144145146-147148149-150151152-1531155156

240 PQFP1571581591601611621631165166167168169170171172173174175176177178‘179180

Notes:1.2.3.4.PWR = Pins connected to power plane = F1, E4/E5, L2, R4, K15, L12, E14, A12.GND = Pins connected to ground plane = L4, M4, N9, N10, E12, D12, C7, C6.85 = Pin 85 on AT6005.

85 = Pin 85 on AT6003 and AT6010.

AT6000(LV) Series

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AT6000(LV) Series

Pinout Assignment

Top Side (Right to Left)

AT6002M1-I/O48(A)------I/O47(A)--I/O46(B)I/O45(A)--I/O44(B)I/O43(A)-I/O42(B)I/O41(A)I/O40(B)-I/O39(A)-GNDI/O38(A)--I/O37(A) or A16CLOCKI/O36(B) or A15-I/O35(A) or A14-VCC

AT6003M1-I/O60(A)I/O59(B)----I/O58(A)I/O57(A)--I/O56(A)I/O55(A)--I/O(B)I/O53(A)-I/O52(B)I/O51(A)I/O50(B)-I/O49(A)I/O48(B)GNDI/O47(A)-I/O46(B)I/O45(A) or A16CLOCKI/O44(B) or A15-I/O43(A) or A14-VCC

AT6005M1-I/O(A)-----I/O53(A)I/O52(A)--I/O51(A)I/O50(A)--I/O49(A)I/O48(A)-I/O47(A)I/O46(A)I/O45(A)-I/O44(A)I/O43(A)GNDI/O42(A)--I/O41(A) or A16CLOCKI/O40(A) or A15-I/O39(A) or A14-VCC

AT6010M1I/O102(A)I/O101(A)I/O100(A)I/O99(B)VCCI/O98(A)GNDI/O97(A)I/O96(A)I/O95(B)I/O94(A)I/O93(A)I/O92(A)I/O91(B)I/O90(A)I/O(A)I/O88(A)I/O87(B)I/O86(A)I/O85(A)I/O84(A)I/O83(B)I/O82(A)I/O81(A)GNDI/O80(A)I/O79(B)I/O78(A)I/O77(A) or A16CLOCKI/O76(A) or A15I/O75(B)I/O74(A) or A14VDDVCC

84 PLCC75-76------77---78---79--80--81-8283--8412-3-4

100 VQFP76-77------78---79--8081--8283-84-8586--8788-90-91

132 PQFP117-118-----119120--121122--123124-125126127-128129130131--13212-3-4

144 TQFP109-110111----112113--114115--116117-118119120-121122123124-125126127128-129-130

180 CPGAD11D10D9A14-PWR(1)A13GND(2)A11A10-A9B13B12-B11B10B9-C12C11C10-C9D8GND(2)D7-D6D5E8D4-C8PWR(1)PWR(1)

208 PQFP157158159160-1611621631165-166167168-169170171-172173174175176177178179180181182183184185186187188

240 PQFP1811821831841851861871881190191192193194195196197198199200201202203204205206207208209210211212213214215216

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Pinout Assignment (Continued)

Top Side (Right to Left)

AT6002I/O34(A) or A13I/O33(B)-I/O32(A) or A12I/O31(B)--I/O30(A) or A11--GND-I/O29(A) or A10I/O28(B)--I/O27(A) or A9I/O26(B)---I/O25(A) or A8-M0

AT6003I/O42(A) or A13I/O41(B)-I/O40(A) or A12I/O39(B)--I/O38(A) or A11I/O37(B)-GND-I/O36(A) or A10I/O35(B)--I/O34(A) or A9I/O33(A)--I/O32(B)I/O31(A) or A8-M0

AT6005I/O38(A) or A13I/O37(A)-I/O36(A) or A12I/O35(A)--I/O34(A) or A11I/O33(A)-GND-I/O32(A) or A10I/O31(A)--I/O30(A) or A9I/O29(A)---I/O28(A) or A8-M0

AT6010I/O73(A) or A13I/O72(A)I/O71(B)I/O70(A) or A12I/O69(A)I/O68(A)I/O67(B)I/O66(A) or A11I/O65(A)I/O(A)GNDI/O63(B)I/O62(A) or A10I/O61(A)I/O60(A)I/O59(B)I/O58(A) or A9I/O57(A)I/O56(A)I/O55(B)I/O(A)I/O53(A) or A8I/O52(A)M0

84 PLCC5--6---7----8---9----10-11

100 VQFP92--9394--95----9697--98----99-100

132 PQFP56-78--910-11-1213--1415---16-17

144 TQFP131132-133134--135136-137-138139--140141--142143-144

180 CPGAC5C4-C3B8B7-B6B5B4GND(2)

-B3B2A8-A7A6A5-A4A3A2A1

208 PQFP1190191192193194-195196197198-199200201-202203204-205206-207208

240 PQFP217218219220221222223224225226227228229230231232233234235236237238239240

Notes:1.PWR = Pins connected to power plane = F1, E4/E5, L2, R4, K15, L12, E14, A12.2.GND = Pins connected to ground plane = L4, M4, N9, N10, E12, D12, C7, C6.

AT6000(LV) Series

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AC Timing Characteristics – 5V Operation

AT6000(LV) Series

Delays are based on fixed load. Loads for each type of device are described in the notes. Delays are in nanoseconds.Worst case: VCC = 4.75V to 5.25V. Temperature = 0°C to 70°C.

Cell FunctionWire(4)NANDXORANDMUXD-Flip-flop(5)D-Flip-flop(5)D-Flip-flopBus DriverRepeaterColumn ClockColumn ResetClock Buffer(5)Reset Buffer(5)TTL Input(1)CMOS Input(2)Fast Output(3)Slow Output(3)Output Disable(5)Fast Enable(3)(5)Slow Enable(3)(5)DeviceCell(6)Bus(6)

Column Clock(6)Notes:

1.2.3.4.5.6.7.

ParametertPD (max)(4)tPD (max)tPD (max)tPD (max)tPD (max)tsetup (min)thold (min)tPD (max)tPD (max)tPD (max)tPD (max)tPD (max)tPD (max)tPD (max)tPD (max)tPD (max)tPD (max)tPD (max)tPXZ (max)tPXZ (max)tPXZ (max)

Cell Types

Wire, XWire, Half-adder, Flip-flop

Wire, XWire, Half-adder, Flip-flop, RepeaterColumn Clock Driver

FromA, B, LA, B, LA, B, LA, B, LA, BLA, B, LCLKCLKAL, EL, EGCLK, A, ESGRES, A, ENCLOCK PINRESET PIN

I/OI/OAALLL

ToA, BBABAACLKA, B, LALELCLKRESGCLKGRESAAI/O PINI/O PINI/O PINI/O PINI/O PIN

Load Definition(7)

111111--123233--3344444

-10.81.61.81.71.72.11.501.52.01.31.71.81.81.61.51.01.33.37.53.13.88.2OutputsA, BLCLK

-21.22.22.42.22.33.02.002.02.61.62.12.42.42.01.91.21.43.58.03.34.08.5

-41.83.24.03.24.04.93.003.04.02.33.03.03.02.92.81.52.36.012.05.56.512.5ICC (max)4.5 µA/MHz2.5 µA/MHz40 µA/MHz

Unitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns

TTL buffer delays are measured from a VIH of 1.5V at the pad to the internal VIH at A. The input buffer load is constant.

CMOS buffer delays are measured from a VIH of 1/2 VCC at the apd to the internal VIH at A. The input buffer load is constant. Buffer delay is to a pad voltage of 1.5V with one output switching.Max specifications are the average of mas tPDLH and tPDHL.

Parameter based on characterization and simulation; not tested in productionExact power calculation is available in an Atmel application note.

Load Definition: 1 = Load of one A or B input; 2 = Load of one L input; 3 = Constant Load; 4 = Tester Load of 50 pF.

= Preliminary Information

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AC Timing Characteristics – 3.3V Operation

Delays are based on fixed load. Loads for each type of device are described in the notes. Delays are in nanoseconds.Worst case: VCC = 3.0V to 3.6V. Temperature = 0°C to 70°C.

Column Clock(6)Notes:

1.2.3.4.5.6.7.

Cell Types

Wire, XWire, Half-adder, Flip-flop

Wire, XWire, Half-adder, Flip-flop, RepeaterColumn Clock Driver

FromA, B, LA, B, LA, B, LA, B, LA, BLA, B, LCLKCLKAL, EL, EGCLK, A, ESGRES, A, ENCLOCK PINRESET PIN

I/OI/OAALLL

ToA, BBABAACLKA, B, LALELCLKRESGCLKGRESAAI/O PINI/O PINI/O PINI/O PINI/O PIN

OutputsA, BLCLK

Load Definition(7)

111111--123233453366666

-41.83.24.03.24.04.93.003.04.02.33.03.03.02.92.81.52.36.012.05.56.512.5

ICC (max)2.3 µA/MHz1.3 µA/MHz20 µA/MHz

Unitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns

TTL buffer delays are measured from a VIH of 1.5V at the pad to the internal VIH at A. The input buffer load is constant.

Parameter based on characterization and simulation; not tested in productionExact power calculation is available in an Atmel application note.

Load Definition: 1 = Load of one A or B input; 2 = Load of one L input; 3 = Constant Load; 4 = Load of 28 Clock Columns; 5 = Load of 28 Reset Columns; 6 = Tester Load of 50 pF.

AT6000(LV) Series

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AT6000(LV) Series

Absolute Maximum Ratings*

Supply Voltage (VCC)........................................-0.5V to + 7.0VDC Input Voltage (VIN)...............................-0.5V to VCC + 0.5VDC Output Voltage (VON)...........................-0.5V to VCC + 0.5VStorage Temperature Range

(TSTG)...........................................................-65°C to +150°CPower Dissipation (PD).............................................1500 mWLead Temperature (TL)

(Soldering, 10 sec.)........................................................260°CESD (RZAP = 1.5K, CZAP = 100 pF).................................2000V

*NOTICE:

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. These are stress rating only and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. Exposure to Absolute Maximum Rating conditions for

extended periods of time may affect device reli-ability.

DC and AC Operating Rage – 5V Operation

AT6002-2/4AT6003-2/4AT6005-2/4AT6010-2/4Commercial

Operating Temperature (Case)VCC Power SupplyInput Voltage Level(TTL)

Input Voltage Level(CMOS)

Input Signal Transition Time (TIN)

High (VIHT)Low (VILT)High (VIHC)Low (VILC)

0°C - 70°C5V ± 5%

2.0V-VCC

0V - 0.8V70% - 100% VCC0 - 30% VCC50 ns (max)

AT6002-2/4

AT6003-2/4AT6005-2/4AT6010-2/4Industrial-40°C - 85°C5V ± 10%2.0V - VCC0V - 0.8V70% - 100% VCC0 - 30% VCC50 ns (max)

AT6002-2/4AT6003-2/4AT6005-2/4AT6010-2/4Military-55°C - 125°C5V ± 10%2.0V - VCC0V - 0.8V70% - 100% VCC0 - 30% VCC50 ns (max)

DC and AC Operating Rage – 3.3V Operation

AT6002-2/4, AT6003-2/4AT6005-2/4, AT6010-2/4

Commercial

Operating Temperature (Case)VCC Power SupplyInput Voltage Level(TTL)

Input Voltage Level(CMOS)

Input Signal Transition Time (TIN)

High (VIHT)Low (VILT)High (VIHC)Low (VILC)

0°C - 70°C3.3V ± 5%

2.0V-VCC

0V - 0.8V70% - 100% VCC0 - 30% VCC50 ns (max)

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DC Characteristics – 5V Operation

SymbolVIH

Parameter

High-level Input Voltage

ConditionsCommercial

CMOSTTLCMOSTTL

IOH = -4 mA, VCC minIOH = -16 mA, VCC minIOL = 4 mA, VCC minIOL = 16 mA, VCC min

Min70% VCC

2.0003.93.0

0.40.510

-10-500

50010MaxVCCVCC30% VCC

0.8

UnitsVVVVVVVVµAµAµAµAµAµAµApF

VIL

Low-level Input VoltageCommercial

VOH

High-level Output VoltageCommercial

VOL

Low-level Output VoltageHigh-level TristateOutput Leakage CurrentHigh-level TristateOutput Leakage CurrentHigh-level Input CurrentLow-level Input CurrentPower ConsumptionInput Capacitance

Commercial

IOZHVO = VCC (max)

Without Pull-up, VO = VSSWith Pull-up, VO = VSSVIN = VCC (max)

Without Pull-up, VIN = VSSWith Pull-up, VIN = VSS

Without Internal Oscillator (Standby)All Pins

IOZLIIHIILICCCIN

AT6000(LV) Series

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AT6000(LV) Series

DC Characteristics – 3.3V Operation

SymbolVIH

Parameter

High-level Input Voltage

ConditionsCommercial

CMOSTTLCMOSTTL

IOH = -2 mA, VCC minIOH = -6 mA, VCC minIOL = +2 mA, VCC minIOL = +6 mA, VCC min

Min70% VCC

2.0002.42.0

0.40.510

-10-500

20010MaxVCCVCC30% VCC

0.8

UnitsVVVVVVVVµAµAµAµAµAµAµApF

VIL

Low-level Input VoltageCommercial

VOH

High-level Output VoltageCommercial

VOL

Low-level Output VoltageHigh-level TristateOutput Leakage CurrentHigh-level TristateOutput Leakage CurrentHigh-level Input CurrentLow-level Input CurrentPower Consumption

Commercial

IOZHVO = VCC (max)

Without Pull-up, VO = VSSWith Pull-up, VO = VSSVIN = VCC (max)

Without Pull-up, VIN = VSSWith Pull-up, VIN = VSS

Without Internal Oscillator (Standby)

IOZLIIHIILICCCIN(1)Note:Input CapacitanceAll Pins

1.Parameter based on characterization and simulation; it is not tested in production.Device Timing: During Operation

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Ordering Information – AT6002

Usable Gates6,000

SpeedGrade (ns)

Ordering CodeAT6002-2ACAT6002A-2ACAT6002-2JCAT6002-2QCAT6002-2AIAT6002A-2AIAT6002-2JIAT6002-2QI

6,000

AT6002-4ACAT6002A-4ACAT6002-4JCAT6002-4QCAT6002LV-4ACAT6002ALV-4ACAT6002LV-4JCAT6002LV-4QCAT6002-4AIAT6002A-4AIAT6002-4JIAT6002-4QI

Package100A144A84J132Q100A144A84J132Q100A144A84J132Q100A144A84J132Q100A144A84J132Q

Operation Range5V Commercial(0°C to 70°C)

5V Industrial(-40°C to 85°C)

5V Commercial(0°C to 70°C)

3.3V Commercial(0°C to 70°C)

5V Industrial(-40°C to 85°C)

Package Type

84J100A132Q144A208Q240Q

84-lead, Plastic J-leaded Chip Carrier (PLCC)

100-lead, Very Thin (1.0 mm) Plastic Gull-Wing Quad Flat Package (VQFP)132-lead, Bumpered Plastic Gull-Wing Quad Flat Package (BQFP)144-lead, Thin (1.4 mm) Plastic Gull-Wing Quad Flat Package (TQFP)208-lead, Plastic Gull-Wing Quad Flat Package (PQFP)240-lead, Plastic Gull-Wing Quad Flat Package (PQFP)

AT6000(LV) Series

元器件交易网www.cecb2b.com

AT6000(LV) Series

Ordering Information – AT6003

Usable Gates9,000

SpeedGrade (ns)

Ordering CodeAT6003-2ACAT6003A-2ACAT6003-2JCAT6003-2QCAT6003-2AIAT6003A-2AIAT6003-2JIAT6003-2QI

9,000

AT6003-4ACAT6003A-4ACAT6003-4JCAT6003-4QCAT6003LV-4ACAT6003ALV-4ACAT6003LV-4JCAT6003LV-4QCAT6003-4AIAT6003A-4AIAT6003-4JIAT6003-4QI

Package100A144A84J132Q100A144A84J132Q100A144A84J132Q100A144A84J132Q100A144A84J132Q

Operation Range5V Commercial(0°C to 70°C)

Industrial(-40°C to 85°C)

5V Commercial(0°C to 70°C)

3.3V Commercial(0°C to 70°C)

5V Industrial(-40°C to 85°C)

Package Type

84J100A132Q144A208Q240Q

84-lead, Plastic J-leaded Chip Carrier (PLCC)

元器件交易网www.cecb2b.com

Ordering Information – AT6005

Usable Gates15,000

SpeedGrade (ns)

Ordering CodeAT6005-2ACAT6005A-2ACAT6005-2JCAT6005-2QCAT6005A-2QCAT6005-2AIAT6005A-2AIAT6005-2JIAT6005-2QIAT6005A-2QI

15,000

AT6005-4ACAT6005A-4ACAT6005-4JCAT6005-4QCAT6005A-4QCAT6005LV-4ACAT6005ALV-4ACAT6005LV-4JCAT6005LV-4QCAT6005ALV-4QCAT6005-4AIAT6005A-4AIAT6005-4JIAT6005-4QIAT6005A-4QI

Package100A144A84J132Q208Q100A144A84J132Q208Q100A144A84J132Q208Q100A144A84J132Q208Q100A144A84J132Q208Q

Operation Range5V Commercial(0°C to 70°C)

Industrial(-40°C to 85°C)

5V Commercial(0°C to 70°C)

3.3V Commercial(0°C to 70°C)

5V Commercial(-40°C to 85°C)

Package Type

84J100A132Q144A208Q240Q

84-lead, Plastic J-leaded Chip Carrier (PLCC)

AT6000(LV) Series

元器件交易网www.cecb2b.com

AT6000(LV) Series

Ordering Information – AT6010

Usable Gates30,000

SpeedGrade (ns)

Ordering CodeAT6010-2JCAT6010A-2ACAT6010-2QCAT6010A-2QCAT6010H-2QCAT6010-2JIAT6010A-2AIAT6010-2QIAT6010A-2QIAT6010H-2QI

30,000

AT6010A-4ACAT6010-4QCAT6010-4JCAT6010A-4QCAT6010H-4QCAT6010ALV-4ACAT6010LV-4QCAT6010LV-4JCAT6010ALV-4QCAT6010HLV-4QCAT6010A-4AIAT6010-4QIAT6010-4JIAT6010A-4QIAT6010H-4QI

Package84J144A132Q208Q240Q84J144A132Q208Q240Q144A132Q84J208Q240Q144A132Q84J208Q240Q144A132Q84J208Q240Q

Operation Range5V Commercial(0°C to 70°C)

Industrial(-40°C to 85°C)

5V Commercial(0°C to 70°C)

3.3V Commercial(0°C to 70°C)

5V Industrial(-40°C to 85°C)

Package Type

84J100A132Q144A208Q240Q

84-lead, Plastic J-leaded Chip Carrier (PLCC)

元器件交易网www.cecb2b.com

Atmel Headquarters

Corporate Headquarters

2325 Orchard ParkwaySan Jose, CA 95131TEL (408) 441-0311FAX (408) 487-2600

Atmel Operations

Atmel Colorado Springs

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13106 Rousset CedexFrance

TEL (33) 4-4253-6000FAX (33) 4-4253-6001

Europe

Atmel U.K., Ltd.

Coliseum Business CentreRiverside Way

Camberley, Surrey GU15 3YLEngland

TEL (44) 1276-686-677FAX (44) 1276-686-697Atmel Asia, Ltd.Room 1219

Chinachem Golden Plaza77 Mody Road TsimhatsuiEast Kowloon

TEL (852) 2721-9778FAX (852) 2722-1369Atmel Japan K.K.

9F, Tonetsu Shinkawa Bldg.1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033Japan

TEL (81) 3-3523-3551FAX (81) 3-3523-7581

Atmel Rousset

Asia

Japan

Fax-on-Demand

North America:1-(800) 292-8635International:1-(408) 441-0732

e-mail

literature@atmel.com

Web SiteBBS

http://www.atmel.com1-(408) 436-4309

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility forany errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time withoutnotice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop-erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products arenot authorized for use as critical components in life support devices or systems.

Marks bearing ® and/or ™ are registered trademarks and trademarks of Atmel Corporation.Terms and product names in this document may be trademarks of others.

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