FPGA可编程逻辑器件芯片XC3S400A-5FG320I中文规格书

Date

04/05/2017

Version

1.4

Revision

•Added MicroBlaze MCS ECC in all Core Architecture chapters.

•Added system reset pin description to all Pin Rules section in Designingwith the Core chapter.•Updated Advanced Options figure in Design Flow Steps chapters.•Removed Synplify Pro Black Box sections in all Example Design chapters.•Added LPDDR3 IP section.DDR3/DDR4

•Updated Notes in DDR3 and DDR4 section in Overview chapter.•Added 3DS component support in DDR4 SDRAM section in Overviewchapter.•Updated the Physical Layer bullet in Overview chapter.

•Added CRC for write and 2T timing not supported in DDR4 FeatureSummary.•Added Read and Write VREF Calibration section in Core Architecturechapter.•Added note in ECC in Core Architecture chapter.

•Added Partial Reconfiguration in Core Architecture chapter.•Added SSTL15 in DDR3 Pin Rules section in Designing with the Corechapter.•Added LVCMOS12 in DDR4 Pin Rules section in Designing with the Corechapter.•Added DDR4 4 Gb (x16) app_addr Mapping Options table in Designing withthe Core chapter.•Updated C_S_AXI_SUPPORTS_NARROW_BURST description in AXI4 SlaveInterface Parameters table.•Updated description in app_en in User Interface table.

•Added note in s_axi_awlock and s_axi_arlock rows in AXI4 Slave InterfaceSignals table.•Updated Example 2 code in SLOT0_FUNC_CS section.

•Updated a and b description in Simulating the Performance TrafficGenerator section.QDR II+

•Updated description in qdriip_qvld in Memory Interface Signals table.Traffic Generator

•Added important note in Advanced Traffic Generator section.

UltraScale Architecture-Based FPGAs Memory IP v1.4PG150 January 21, 2021

Appendix C:Additional Resources and Legal Notices

Date

11/30/2016

Version

1.3

Revision

•Updated Advanced Clocking Tab GUIs in Design Flow Steps chapters.•Updated SIM_MODE description in all Simulation Speed sections.•Added PFD formula in M and D Support for Reference Input Clock Speedsections.DDR3/DDR4

•Added Memory Settings in Core Architecture section.•Added Note in the Resets section.

•Updated SIM_MODE description in PHY Only Parameters table.•Updated code in SLOT0_CONFIG and SLOT0_FUNC_CS sections.

•Added PFD formula in M and D Support for Reference Input Clock Speedsection.•Updated stimulus memory description in Modules for Performance TrafficGenerator table.•Added 3DS part description in Stimulus Pattern section.QDR II+

•Added important note in Resets section.

•Added Calibration Sequence descriptions in PHY section.RLDRAM 3

•Added dm description in #2 in RLDRAM 3 Pin Rules section.

UltraScale Architecture-Based FPGAs Memory IP v1.4PG150 January 21, 2021

Appendix C:Additional Resources and Legal Notices

Date

10/05/2016

Version

1.3

Revision

•Added density support in all Feature Summary sections.•Added Reset Sequence sections.•Updated Reset sections.

•Added M and D Support for Reference Input Clock Speed sections.•Updated all Design Flow Steps and Example Design GUIs.DDR3/DDR4

•Updated UltraScale Architecture-Based FPGAs DDR3/DDR4 MemoryInterface Solution figure.•Updated DDR Bus Efficiency table.

•Added SODIMMs and ECC features in Feature Summary.

•Updated maintenance block description in Memory Controller section.•Added ECC Port Description section in ECC section.•Updated ECC Block Diagram in ECC Module section.•Updated MicroBlaze in PHY Module table.•Updated Address Parity section.

•Added 0x9 to DQS Gate description in Error Signal Descriptions table.•Added description and updated Status Port Bits title in XSDB Status SignalDescriptions table.•Updated END_ADDR0/1 description in Save Restore and Self-Refreshsections.•Added Clamshell Topology and Migration sections.•Updated User Interface table.

•Added Group to DDR4 ROW_COLUMN_LRANK_BANK and DDR4ROW_LRANK_COLUMN_BANK tables.•Added Payload width in app_wdf_data[APP_DATA_WIDTH – 1:0] section.•Updated description in Read Priority (RD_PRI_REG) section.•Updated ECC Control Register Map table.

•Added Important Note in Pin and Bank Rules section.

•Updated bit names in Correctable Error First Failing Address [63:32]Register table.

UltraScale Architecture-Based FPGAs Memory IP v1.4PG150 January 21, 2021