LM98725 3 Channel, 16-Bit, 81 MSPS Analog Front End with LVDS/CMOS Output, Integrated CCD/CIS Sensor Timing Generator and Spread Spectrum Clock Generation
Literature Number: SNAS474D
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LM98725
3 Channel, 16-Bit, 81 MSPS Analog Front End with LVDS/CMOS Output, Integrated CCD/CIS Sensor TimingGenerator and Spread Spectrum Clock Generation
General Description
The LM98725 is a fully integrated, high performance 16-Bit,81 MSPS signal processing solution for digital color copiers,scanners, and other image processing applications. High-speed signal throughput is achieved with an innovative archi-tecture utilizing Correlated Double Sampling (CDS), typicallyemployed with CCD arrays, or Sample and Hold (S/H) inputs(for higher speed CCD or CMOS image sensors). The signalpaths utilize 8 bit Programmable Gain Amplifiers (PGA), a+/-9-Bit offset correction DAC and independently controlledDigital Black Level correction loops for each input. The PGAand offset DAC are programmed independently allowingunique values of gain and offset for each of the three analoginputs. The signals are then routed to a 81MHz high perfor-mance analog-to-digital converter (ADC). The fully differentialprocessing channel shows exceptional noise immunity, hav-ing a very low noise floor of -74dB. The 16-bit ADC hasexcellent dynamic performance making the LM98725 trans-parent in the image reproduction chain.
A very flexible integrated Spread Spectrum Clock Generation(SSCG) modulator is included to assist with EM complianceand reduce system costs.
grated Sensor Timing Generator and Spread Spectrum Clock GenerationFeatures
■■■■■■■■
LVDS/CMOS Outputs
LVDS/CMOS/Crystal Clock Source with PLL MultiplicationIntegrated Flexible Spread Spectrum Clock GenerationCDS or S/H Processing for CCD or CIS sensors
Independent Gain/Offset Correction for Each ChannelAutomatic per-Channel Gain and Offset CalibrationProgrammable Input Clamp Voltage
Flexible CCD/CIS Sensor Timing Generator
Key Specifications
■■■■■■■■■■■■■■■■
1.2 or 2.4 Volt Modes
(both with + or - polarity option)
ADC Resolution16-BitADC Sampling Rate81 MSPSINL+17/- 28 LSB (typ)Channel Sampling Rate30/30/27 MSPSPGA Gain Steps256 StepsPGA Gain Range0.62 to 8.3xAnalog DAC Resolution+/-9 BitsAnalog DAC Range+/-307mV or +/-614mVDigital DAC Resolution+/-6 BitsDigital DAC Range-2048 LSB to + 2016 LSBSNR-74dB (@0dB PGA Gain)Power Dissipation755mW (LVDS)Operating Temp0 to 70°CSupply Voltage3.3V Nominal (3.0V to 3.6V range)Maximum Input Level
Applications
■
■■■
Multi-Function Peripherals
High-speed Currency/Check ScannersFlatbed or Handheld Color ScannersHigh-speed Document Scanners
System Block Diagram
30085370
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LM30085301
FIGURE 1. Chip Block Diagram
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72530085302
FIGURE 2. LM98725 Pin Out Diagram
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30085373725Pin1234
NamePHIC2PHIC1SH1CE
I/OOOOI
TypDDDD
ResPUPDPU
Description
Configurable high speed sensor timing output.Configurable high speed sensor timing output.Configurable low speed sensor timing output.Chip Serial Interface Address Setting InputCE LevelVDFloatDGND
Address011000
56789101112131415161718192021222324252627282930313233343536
CALRESETSH_RSDISDOSCLKSENVAAGNDVAVREFBVREFTVAAGNDVCLPVAIBIASAGNDOSRAGNDOSGAGNDOSBCPOFILT2DGNDCPOFILT1DVBINCLK+INCLK-DOUT7/TXCLK+DOUT6/TXCLK-DOUT5/TXOUT2+
IIIIOII OO IO O I I I OIIOOO
DDDDDDDPPPAAPPAPAPAPAPAAPADDDDDD
PDPUPDPD PDPU
Initiate calibration sequence. Leave unconnected or tie to DGND if unused.Active-low master reset. NC when function not being used.External request for an SH interval.Serial Interface Data Input.Serial Interface Data Output.Serial Interface shift register clock.
Active-low chip enable for the Serial Interface.
Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND.Analog ground return.
Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND.Bottom of ADC reference. Bypass with a 0.1μF capacitor to ground.Top of ADC reference. Bypass with a 0.1μF capacitor to ground.
Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND.Analog ground return.
Input Clamp Voltage. Normally bypassed with a 0.1μF , and a 4.7μF capacitor to AGND.An external reference voltage may be applied to this pin.
Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND.Bias setting pin. Connect a 9.0 kOhm 1% resistor to AGND.Analog ground return.
Analog input signal. Typically sensor Red output AC-coupled thru a capacitor.Analog ground return.
Analog input signal. Typically sensor Green output AC-coupled thru a capacitor.Analog ground return.
Analog input signal. Typically sensor Blue output AC-coupled thru a capacitor.Charge Pump Filter Capacitor. Bypass this supply pin with a 0.1μF capacitor toCPOFILT1.
Digital ground return.
Charge Pump Filter Capacitor. Bypass this supply pin with a 0.1μF capacitor toCPOFILT2.
Digital Core Voltage bypass. Not an input. Bypass with 0.1μF capacitor to DGND.Clock Input. Non-Inverting input for LVDS clocks or CMOS clock input. CMOS clock isselected when pin 29 is held at DGND, otherwise clock is configured for LVDS operation.Clock Input. Inverting input for LVDS clocks, connect to DGND for CMOS clock.Bit 7 of the digital video output bus in CMOS Mode, LVDS Frame Clock+ in LVDS Mode.Bit 6 of the digital video output bus in CMOS Mode, LVDS Frame Clock- in LVDS Mode.Bit 5 of the digital video output bus in CMOS Mode, LVDS Data Out2+ in LVDS Mode.
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LM3738394041424344454647484950515253545556
DOUT4/TXOUT2-DOUT3/TXOUT1+DOUT2/TXOUT1-DOUT1/TXOUT0+DOUT0/TXOUT0-DGNDVDVC
CLKOUT/SH2SH3RSCPPHIA1PHIA2DGNDVCPHIB1PHIB2SH4SH5
OOOOOO OOOOOO OOOO
DDDDDDPPDDDDDDPPDDDD
PD
Bit 4 of the digital video output bus in CMOS Mode, LVDS Data Out2- in LVDS Mo
Bit 3 of the digital video output bus in CMOS Mode, LVDS Data Out1+ in LVDS M
Bit 2 of the digital video output bus in CMOS Mode, LVDS Data Out1- in LVDS Mo
Bit 1 of the digital video output bus in CMOS Mode, LVDS Data Out0+ in LVDS M
Bit 0 of the digital video output bus in CMOS Mode, LVDS Data Out0- in LVDS MoConfigurable sensor control output.
Power supply for the digital circuits. Bypass this supply pin with 0.1μF capacitor. A s4.7μF capacitor should be used between the supply and the VD, VR and VC pins.
Power supply for the sensor control outputs. Bypass this supply pin with 0.1μF capa
Output clock for registering output data when using CMOS outputs, or a configuralow speed sensor timing output.
Configurable low speed sensor timing output.Configurable high speed sensor timing output.Configurable high speed sensor timing output.Configurable high speed sensor timing output.Configurable high speed sensor timing output.Digital ground return.
Power supply for the sensor control outputs.Bypass this supply pin with 0.1μF capacitor.Configurable high speed sensor timing output.Configurable high speed sensor timing output.Configurable low speed sensor timing output.Configurable low speed sensor timing output.
(I=Input), (O=Output), (IO=Bi-directional), (P=Power), (D=Digital), (A=Analog), (PU=Pull Up with an internal resistor), (PD=Pull Down with an internal resistor
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2)
If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.Supply Voltage (VA,VR,VD,VC)Voltage on Any Input Pin(Not to exceed 4.2V)
Voltage on Any Output Pin
(execpt DVB and not to exceed 4.2V)DVB Output Pin Voltage
Input Current at any pin other thanSupply Pins (Note 3)
Package Input Current (except SupplyPins) (Note 3)
Maximum Junction Temperature (TA)
4.2V−0.3V to(VA + 0.3V)−0.3V to(VA + 0.3V)
2.0V±25 mA
±50 mA150°C
Package Dissipation at TA = 25°C>1.89W(Note 4)
ESD Rating (Note 5) Human Body Model2500V Machine Model250VStorage Temperature−65°C to +150°CSoldering process must comply with NationalSemiconductor’s Reflow Temperature Profile
specifications. Refer to www.national.com/packaging.(Note 6)
725Operating Ratings
Operating Temperature RangeAll Supply Voltage
(Note 1, Note 2)
0°C ≤ TA ≤ +70°C+3.0V to +3.6V
Electrical Characteristics
The following specifications apply for VA = VD = VR = VC = 3.3V, CL = 10pF, and fINCLK = 27MHz unless otherwise specified.Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C.Symbol
Parameter
Conditions
Min(Note 9)2.0
Typ(Note 8)
0.6 1006530
-65-100-30
3.0
18-2520-25
2.30.1212-1420-25
nA
VVmA
nA
0.21 Max(Note 9)
0.8
Units
CMOS Digital Input DC Specifications (RESETb, SH_R, SCLK, SENb)
VIHVILVIHYSTIIH
Logical “1” Input VoltageLogical “0” Input VoltageLogic Input HysteresisLogical “1” Input Current
VIH = VD
RESET,SENSH_R, SCLK, SDI, CAL
CE
IIL
Logical “0” Input Current
VIL = DGNDRESETSENSH_R, SCLK, SDI, CAL
CE
CMOS Digital Output DC Specifications (SH1 to SH5, RS, CP, PHIA, PHIB, PHIC)
VOHVOLIOSIOZ
Logical “1” Output VoltageLogical “0” Output VoltageOutput Short Circuit CurrentCMOS Output TRI-STATE Current
IOUT = -0.5mAIOUT = 1.6mAVOUT = DGNDVOUT= VDVOUT = DGNDVOUT = VD
CMOS Digital Output DC Specifications (CMOS Data Outputs)
VOHVOLIOSIOZ
Logical “1” Output VoltageLogical “0” Output VoltageOutput Short Circuit CurrentCMOS Output TRI-STATE Current
IOUT = -0.5mAIOUT = 1.6mAVOUT = DGNDVOUT= VDVOUT = DGNDVOUT = VD
LVDS/CMOS Clock Receiver DC Specifications (INCLK+ and INCLK- Pins)
VVmAVV nAμAnA μAnAμA
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LM(Note 9)
VIHL
Differential LVDS ClockHigh Threshold Voltage
VILLVIHCVILCIIHLIILC
Differential LVDS ClockLow Threshold VoltageCMOS Clock
High Threshold VoltageCMOS Clock
Low Threshold VoltageCMOS ClockInput High CurrentCMOS ClockInput Low CurrentDifferential Output VoltageLVDS Output Offset VoltageOutput Short Circuit CurrentVA Analog Supply Current
VOUT = 0V, RL = 100ΩLVDS Output Data FormatLVDS Output Data Format
(Powerdown)CMOS Output Data Format
(40 MHz)
ID
VD Digital Output Driver Supply
Current
LVDS Output Data FormatLVDS Output Data Format
(Powerdown)CMOS Output Data Format(ATE Loading of CMOS Outputs
> 50 pF) (40 MHz)
IC
VC CCD Timing Generator Output
Driver Supply Current
Typical sensor outputs:SH1-SH5, PHIA, PHIB, PHIC,
RS, CP
(ATE Loading of CMOS
Outputs > 50pF)LVDS Output Data FormatLVDS Output Data Format
(Powerdown)CMOS Output Data Format(ATE Loading of CMOS Outputs
> 50pF) (40 MHz)
Input Sampling Circuit Specifications
VIN
Input Voltage Level
CDS Gain=1x, PGA Gain=1xCDS Gain=2x, PGA Gain= 1x
RL = 100Ω
VCM (LVDS Input Common Mode
Voltage)= 1.25V
INCLK- = DGND
2.0 -135
(Note 8)
(Note 9)200
mV
-200 230-120
0.8260
mV
V
V
μA
μA
LVDS Output DC Specifications
VODVOSIOSIA
RL = 100Ω
2801.08
3901.208.51523.6136768.546
4901.33 1806168941768
mV
V
mA
Power Supply Specifications
mA
mA
mA
mA
mA
mA
14mA
PWRAverage Power Dissipation
75540600
88570740
mW
mW
mW
2.31.22
Vp-
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(Note 9)
IIN_SH
Sample and Hold ModeInput Leakage Current
CSH
Sample/Hold Mode
Equivalent Input Capacitance
CDS Mode
Input Leakage CurrentCLPIN Switch Resistance(OSX to VCLP Node)
VCLP Voltage 000VCLP Voltage 001VCLP Voltage 010
VVCLP
VCLP Voltage 011VCLP Voltage 100VCLP Voltage 101VCLP Voltage 110VCLP Voltage 111
ISC
VCLP DAC Short Circuit Output
Current
ResolutionMonotonicityOffset Adjustment RangeReferred to AFE Input
Offset Adjustment RangeReferred to AFE Output
DNLINL
DAC LSB Step SizeDifferential Non-LinearityIntegral Non-Linearity
Source Followers OffCDS Gain = 1x
OSX = VA (OSX = AGND)Source Followers OffCDS Gain = 2x
OSX = VA (OSX = AGND)Source Followers OnCDS Gain = 2x
OSX = VA (OSX = AGND)
CDS Gain = 1xCDS Gain = 2xSource Followers OffOSX = VA (OSX = AGND)
(-200) (-290) (-250) (-250)
(Note 8)32(-165) 55(-240) 20(-50) 2.5410(-50)16
(Note 9)50 70 250 250 55
μA
725μA
nA
pFpFnAΩ
IIN_CDSRCLPIN
VCLP Reference Circuit Specifications
VCLP Voltage Setting = 000VCLP Voltage Setting = 001VCLP Voltage Setting = 010VCLP Voltage Setting = 011VCLP Voltage Setting = 100VCLP Voltage Setting = 101VCLP Voltage Setting = 110VCLP Voltage Setting = 1110001 xxxxb VCLP Config.
Register =
CDS Gain = 1x
Minimum DAC Code = 0x000Maximum DAC Code = 0x3FFCDS Gain = 2x
Minimum DAC Code = 0x000Maximum DAC Code = 0x3FFMinimum DAC Code = 0x000Maximum DAC Code = 0x3FFCDS Gain = 1xReferred to AFE Output
0.85VA0.9VA0.95VA0.6VA0.55VA0.4VA0.35VA0.15VA30
VVVVVVVVmA
Black Level Offset DAC Specifications
10 -614614 -307307 1.2(32)+0.74/-0.37+0.72/-0.5688.318.4
mV
mV
-16130+17500
+2.4+2.5
Bits
Guaranteed by characterization
-17500+16130
-0.84-2.5
LSBmV(LSB)LSBLSB
PGA Specifications
Gain ResolutionMonotonicityMaximum Gain
CDS Gain = 1xCDS Gain = 1x
7.717.7
8.818.9
BitsV/VdB
Guaranteed by characterization
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NATIONAL-SEMICONDUCTOR
LM98725CCMT/NOPBLM98725CCMTX/NOP
B
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